Patent · US Active

Architecture, system, method, and computer-accessible medium for partial-scan testing

US9599671B2 · kind B2 · utility

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30Claims
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Assignee

Inventor

Key dates

Filing dateFeb 8, 2012
Grant dateMar 21, 2017
Priority date—
Expiry dateFeb 16, 2035

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318586
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

Exemplary method, computer-accessible medium, test architecture, and system can be provided for a partial-scan test of at least one integrated circuit. For example, it is possible to obtain a plurality of test cubes using a first combinational automatic test pattern generation (ATPG) and identify at least one flip-flop of the integrated circuit using the test cubes to convert to a non-scan flip-flop and facilitate the partial-scan test to utilize the cubes without a utilization of a sequential ATPG or a second combinational ATPG.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.