Patent · US Active

System for dynamic compilation of at least one instruction flow

US9600252B2 · kind B2 · utility

0Cited by

3References

9Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Alexandre CARBON · Les Ulis, FR
Yves Lhuiller · Palaiseau, FR

Key dates

Filing date	Feb 19, 2014
Grant date	Mar 21, 2017
Priority date	—
Expiry date	May 30, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/4552
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A compilation system for at least one instruction flow to be executed on a target circuit comprises a hardware acceleration circuit performing the functions of loading a set of at least one portion of said flow to a memory internal to the circuit and of decoding the set; the instructions resulting from the loading and from the decoding being transmitted to a programmable core operating in parallel to the hardware acceleration circuit, the programmable core producing the transcription of the decoded instructions into a machine code suitable for execution on the target circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.