Automated flip-flop insertions in physical design without perturbation of routing
US9600614B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Mar 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method of automatically performing flip-flop insertions for each net in a logic interface by using the RTL-estimated maximum count as a limit. Based on the timing analysis on the physical layout, a flip-flop insertion count needed for each net is derived and candidate locations for insertions are automatically detected. A set of constraints is applied to identify ineligible locations for flip-flop insertions. If more flip-flop insertions than the count limit are needed to satisfy the timing requirements for a net, timing-related variables are iteratively adjusted using the current layout until the timing requirements can be satisfied using the RTL count limit. If all the nets in the interface need fewer flip-flop insertions than the RTL count limit, the information can be fed back to update the RTL count limit. Each net is then parsed and flip-flops are inserted at appropriated locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.