Assuring chip reliability with automatic generation of drivers and assertions
US9600616B1 · kind B1 · utility
1Cited by
1References
20Claims
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Key dates
| Filing date | Sep 13, 2016 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Sep 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.