Repeater insertions providing reduced routing perturbation caused by flip-flop insertions
US9600620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Jun 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method of automatically performing repeater insertions in physical design of an integrated circuit. Repeaters are inserted in interconnects in a staggered fashion and spaced apart to accommodate potential flip-flop insertions. The sufficient spacing between the repeaters in combination with the staggered pattern ensures that flip-flop insertions can be performed at any of the repeater locations without space limitation. When rerouting is needed following a flip-flop insertion on an interconnect, automatic rerouting is performed but restricted to a short and specified region along the interconnect. Thereby, the resulted alteration from the current routing configuration is minimal and deterministic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.