Memory devices with strap cells
US9601162B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2016 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | May 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank. The first data line has a first portion and a second portion, in which the first portion of the first data line is disconnected from the second portion of the first data line, and the second portion of the first data line is configured to couple the first sub-bank to a first input/output (I/O) circuit. The second data line and the first portion of the first data line are configured to couple the second sub-bank to the first I/O circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.