Memory device and computing system including the same
US9601218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2014 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Feb 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.