Method of manufacturing a semiconductor device
US9601351B2 · kind B2 · utility
1Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2014 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Nov 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.