Module arrangement for power semiconductor devices
US9601399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Oct 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A module arrangement for power semiconductor devices, including one or more power semiconductor modules, wherein the one or more power semiconductor modules include a substrate with a first surface and a second surface being arranged opposite to the first surface, wherein the substrate is at least partially electrically insulating, wherein a conductive structure is arranged at the first surface of the substrate, wherein at least one power semiconductor device is arranged on the conductive structure and electrically connected thereto, wherein the one or more modules includes an inner volume for receiving the at least one power semiconductor device which volume is hermetically sealed from its surrounding by a module enclosure, wherein the module arrangement includes an arrangement enclosure at least partly defining a volume for receiving the one or more modules, and wherein the arrangement enclosure seals covers the volume.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.