Manufacturing method of array substrate
US9601528B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Apr 20, 2016 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Apr 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a manufacturing method of an array substrate, comprising steps of: forming a gate and a gate line on a substrate; forming a gate insulating layer on the gate and the gate line; forming a pixel electrode on the gate insulating layer; and forming a first connecting via in a portion of the gate insulating layer in a non-display region and corresponding to the gate line, wherein the first connecting via is configured to connect a scanning signal trace to the gate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.