Semiconductor device for reducing gate wiring length
US9601572B2 · kind B2 · utility
0Cited by
9References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Apr 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate pad and a source pad are disposed on a semiconductor layer. The gate pad is disposed at the center portion of the semiconductor layer and has the shape of a circle centered on the center of the semiconductor layer as viewed in plan. The source pad is disposed so as to surround the gate pad, and has the shape of a circular ring centered on the center of the semiconductor layer as viewed in plan. A plurality of unit cells that compose a trench type MOSFET element are formed in the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.