Semiconductor device for reducing propagation time of gate input signals
US9601573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Apr 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate pad is disposed on a semiconductor layer composed of an n+ type substrate, an n− type epitaxial layer, and a p− type body layer. The gate pad is disposed at the center portion of the semiconductor layer as viewed in plan. A plurality of unit cells that compose a trench type MOSFET element are provided in the semiconductor layer. The plurality of unit cells are arranged in the radial direction about the gate pad as viewed in plan. A gate electrode of a unit cell (center-side unit cell) that is proximate to the gate pad is electrically connected to the gate pad. Gate electrodes of unit cells that are adjacent to each other in the radial direction are connected to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.