Amplifier topology for envelope tracking
US9602059B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2014 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Mar 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier has an input port for receiving an input signal and an envelope port for receiving an envelope signal indicative of an envelope of the input signal, and an output port for delivering an amplified signal. The amplifier has a first transistor and a second transistor. A first biasing circuit is coupled to the envelope port and is arranged to generate a first bias voltage dependent on the envelope signal. A summing stage is coupled to the input port for receiving the input signal, to the first biasing circuit for receiving the first bias voltage, and to the gate of the first transistor. A second biasing circuit is coupled between the envelope port and the gate of the second transistor, and is arranged to generate a second bias voltage dependent on the envelope signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.