Power amplifier architectures with input power protection circuits
US9602060B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2014 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Jul 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G2201/106
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.