Double half latch for clock gating
US9602086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Aug 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal. The double half-latch circuit is transparent to the state changes of the local input enable signal when the clock signal is low and opaque to state changes of the local input enable signal when the clock signal is high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.