Interleaved successive approximation register analog to digital converter
US9602116B1 · kind B1 · utility
29Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2016 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Jan 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.