Background estimation of comparator offset of an analog-to-digital converter
US9602121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Jul 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.