Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 64-symbol mapping, and bit interleaving method using same
US9602138B2 · kind B2 · utility
14Cited by
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3Claims
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Key dates
| Filing date | Feb 19, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | May 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.