System and method for accelerating network applications using an enhanced network interface and massively parallel distributed processing
US9602437B1 · kind B1 · utility
Inventor
Key dates
| Filing date | Oct 3, 2013 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Oct 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9084
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system comprises a network interface to receive a stream of packets from a network, insert each of the packets into a buffer in memory of a graphics processing unit using direct memory access, assign each of the packets an index representing an offset indicating a location in the memory of the graphics processing unit, determine that a pre-configured buffer flow capacity has been reached regarding a first buffer in the graphics processing unit, and transmit an interrupt to the graphics processing unit corresponding to the pre-configured buffer flow capacity regarding the first buffer in the graphics processing unit. The graphics processing unit is connected to the network interface over a bus and starts a first kernel specific to the first buffer in response to the interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.