Failure management in a vehicle
US9604585B2 · kind B2 · utility
7Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2015 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Mar 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05D1/0077
- WIPO fieldTransport
- WIPO sectorMechanical engineering
Abstract
A system includes first and second failsafe devices. Each of the failsafe devices includes a processor and a memory. The memory stores instructions executable by the processor for performing at least one of detecting a fault and providing a communication concerning a fault. The system further includes an arbitration bus connecting the first and second failsafe devices. The communication concerning the fault may be provided from a first one of the first and second failsafe devices to a second one of the first and second failsafe devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.