Method and apparatus for asynchronous processor based on clock delay adjustment
US9606801B2 · kind B2 · utility
4Cited by
22References
14Claims
0Family size
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Key dates
| Filing date | Sep 8, 2014 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Apr 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/3883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.