Apparatus and method for detecting clock tampering
US9607153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Jul 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.