Semiconductor device comprising power elements in juxtaposition order
US9607945B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2015 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Sep 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and arranged such that the power elements belonging to different power elements are arranged in a repetitive sequential order. The IC chip of the semiconductor device is formed to have output wires extending from the respective divisional elements connected to corresponding output pads without crossing other output wires. Arranged on the IC chip are output bumps in association with the respective output pads. A rewiring layer is provided having output coupling wires for connecting together the bumps that belong to the same power element and connecting them further to an external output electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.