Sampling circuit
US9608603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2015 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Feb 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sampling circuit includes a first latch, a second latch and a signal transition detector. The first latch is disposed on an upstream side of a logic circuit. The second latch is disposed on a downstream side of the logic circuit. The first latch and the second latch respectively switch to opposite states of an opaque state or a transparent state according to trigger signals generated by a reference clock and a control clock. The signal transition detector is configured for detecting whether the signal outputted by the logic circuit is in error or not and outputting a corresponding control clock. The above-mentioned sampling circuit can delay switching the second latch to the opaque state and switching the first latch to the transparent state to correct sampling when a timing error occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.