Segmented successive approximation register (SAR) analog-to-digital converter (ADC) with reduced conversion time
US9608658B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2016 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Feb 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1014
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.