System and method for functional verification of multi-die 3D ICs
US9612277B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Jan 13, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Apr 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318513
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.