High-speed flip-flop with robust scan-in path hold time
US9612281B2 · kind B2 · utility
8Cited by
10References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 20, 2014 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Apr 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A flip-flop is provided that includes a master latch clocked according to a first delay during a normal mode of operation and clocked by a smaller second delay during a scan mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.