Systems and methods generating inter-group and intra-group execution schedules for instruction entity allocation and scheduling on multi-processors
US9612868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2012 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Jan 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for instruction entity allocation and scheduling on multi-processors is provided. In at least one embodiment, a method for generating an execution schedule for a plurality of instruction entities for execution on a plurality of processing units comprises arranging the plurality of instruction entities into a sorted order and allocating instruction entities in the plurality of instruction entities to individual processing units in the plurality of processing units. The method further comprises scheduling instances of the instruction entities in scheduled time windows in the execution schedule, wherein the instances of the instruction entities are scheduled in scheduled time windows according to the sorted order of the plurality of instruction entities and organizing the execution schedule into execution groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.