Patent · US Active

System constraints-aware scheduler for heterogeneous computing architecture

US9612879B2 · kind B2 · utility

4Cited by
0References
20Claims
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Key dates

Filing dateDec 13, 2013
Grant dateApr 4, 2017
Priority date
Expiry dateOct 6, 2034

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02D10/00
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Processors, systems, and methods are arranged to schedule tasks on heterogeneous processor cores. For example, a scheduler is arranged to perform a heuristics based function for allocating operating system tasks to the processor cores. The system includes a hint generator providing a system constraints-aware function that biases the scheduler to select a processor core depending on the change in one or more performance constraint parameters.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.