Peripheral watchdog timer
US9612893B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 11, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Jul 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0706
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a circuit may include a plurality of peripherals and a peripheral watchdog timer circuit coupled to at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to count clock cycles and concurrently to detect activity associated with at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to reset a count in response to detecting the activity. In some embodiments, the peripheral watchdog timer circuit may be configured to generate an alert signal when the count exceeds a threshold count before detecting the activity. In some embodiments, the peripheral watchdog timer circuit is configured to initiate a reset operation when the alert is not serviced within a period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.