FinFET 6T SRAM cell structure
US9613682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Oct 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static memory circuit includes a pull-up transistor, a pull-down transistor, a pass-gate transistor associated with the pull-up and pull-down transistors, and first and second word lines electrically insulated from each other. The pass-gate transistor includes a number of Fins and a gate electrode having a number of first and second gates, each one of the gates is disposed on one of the Fins, the first gates are connected to the first word line, and the second gates are connected to the second word line. During a read operation, one of the first and second word lines is asserted low, so that the beta ratio is greater than or equal to a first predetermined value. During a write operation, one of the first and second word lines is asserted high; so that a gamma ratio is greater than or equal to a second predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.