Burst mode read controllable SRAM
US9613685B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Nov 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller is configured to receive a precharge signal and a word line signal and identify consecutive reads from storage cells accessed via a same one of the word lines. The read controller is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a partial burst mode, precharge the bit lines no more than once during the consecutive reads and charge the same one of the word lines after each read of the consecutive reads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.