Methods for evaluating semiconductor device structures
US9613874B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Dec 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/31745
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods for evaluating semiconductor device structures are provided. In one example, a method includes forming a support layer on a first side of a lamellar sample portion of the semiconductor device structure. The lamellar sample portion has a second side opposite the first side, a target analysis area on or proximate the first side, and a first thickness defined from the first side to the second side. The second side is milled to form a reduced thickness lamellar-supported sample portion that has a milled second side opposite the first side. The support layer is removed from the reduced thickness lamellar-supported sample portion to form a reduced thickness lamellar sample portion having a second thickness that is defined from the first side to the milled second side and that is less than the first thickness. The target analysis area of the reduced thickness lamellar sample portion is evaluated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.