Thin film transistor substrate including a channel length measuring pattern and display panel having the same
US9613876B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Dec 21, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Dec 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor (TFT) substrate includes a base substrate, a TFT disposed on the base substrate. The TFT includes a gate electrode, a semiconductor layer comprising a channel region, and a source electrode and a drain electrode spaced apart from one another by a length of the channel region. The TFT substrate further includes a gate insulating layer disposed between the gate electrode and the semiconductor layer and a measuring pattern configured to measure a length of the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.