Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption
US9614102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2016 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Mar 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/707
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.