Fast fall and rise time current mode logic buffer
US9614530B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 7, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Oct 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current mode logic buffer includes a differential pair of input transistors comprising a first input transistor and a second input transistor, a first output load resistor coupled in series with the first input transistor, a second output load resistor coupled in series with the second input transistor, a first output at a first node between the first output load resistor and the first input transistor, a second output at a second node between the second output load resistor and the second input transistor, a first hold capacitor configured to provide a semi-constant voltage source to the first output via a first low-resistance path, and a second hold capacitor configured to provide a semi-constant voltage source to the second output via a second low-resistance path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.