Asynchronously clocked successive approximation register analog-to-digital converter
US9614540B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Nov 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/125
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The exemplary embodiments relate to an asynchronously clocked successive approximation register analog-to-digital converter (SAR ADC) configured to provide a digital approximation of a sampled input signal as a result of an asynchronous successive approximation operation. The converter includes a regulation circuit configured to determine whether the asynchronous successive approximation operation was performed within a predefined conversion time and to regulate the SAR ADC such that the conversion time of the asynchronous operation is shifted towards the predefined conversion time. The embodiments further relate to a corresponding method and a corresponding design structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.