Circuits and methods providing high-speed data link with equalizer
US9614703B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Sep 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but for the equalizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.