Methods and devices for stressing an integrated circuit

US9618567B2 · kind B2 · utility

Assignee

• EUROPEAN AERONAUTIC DEFENCE AND SPACE COMPANY EADS FRANCE · FR

Inventors

• Florian Moliere · Paris, FR
• Sebastien Morand · Montivilliers, FR
• Alexandre Douin · Nanterre, FR
• Gerard Salvaterra · Clamart, FR
• Christian Binois · Chartres, FR
• Daniel Peyre · Voisins-le-Bretonneux, FR

Key dates

• Filing date: Apr 19, 2011
• Grant date: Apr 11, 2017
• Expiry date: Jun 17, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/48247
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Disclosed is in particular a device (2) for stressing an integrated circuit (1) including an electronic chip (10) mounted in a housing (12), the device including a source (20) of thermal stress. The device (2) also includes a thermally conductive coupling member (22), designed to be thermally coupled to the source (20) of thermal stress during the stressing operation. The coupling member (22) includes an end (220) whose geometry is suitable for being introduced into an aperture with a predefined geometry, to be made in the housing (12) of the integrated circuit (1) so as to thermally couple a coupling face (222) of this end (220) with a face (102) of the electronic chip (10).