Selectively recessed reference plane structure in module tab area of memory module and method for forming selectively recessed reference plane
US9618983B2 · kind B2 · utility
2Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2015 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | May 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/366
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes a signal tab and a power tab spaced apart from each other on a surface layer of a substrate, the signal tab and the power tab defining a module tab area, a reference plane layer below the surface layer, the reference plane layer being recessed below the signal tab and being non-recessed below the power tab, and an insulating layer between the surface layer and the reference plane layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.