Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction
US9619226B2 · kind B2 · utility
6Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Dec 23, 2011 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Nov 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.