Collapsing of multiple nested loops, methods and instructions
US9619229B2 · kind B2 · utility
5Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2012 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Sep 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.