Multi-core memory model and speculative mode processor management
US9619301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2012 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Dec 2, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/528
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a multi-core processor. In one embodiment, each processor core is provided with its own private cache and the device comprises or has access to a common memory, and the method comprises executing a processing thread on a selected first processor core, and implementing a normal access mode for executing an operation within a processing thread and comprising allocating sole responsibility for writing data to given blocks of said common memory, to respective processor cores. The method further comprises implementing a speculative execution mode switchable to override said normal access mode. This speculative execution mode comprises, upon identification of said operation within said processing thread, transferring responsibility for performing said operation to a plurality of second processor cores, and optionally performing said operation on the first processor core as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.