Method and apparatus for optimizing translation of a virtual memory address into a physical memory address in a processor having virtual memory
US9619402B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2013 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Jun 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a device comprising a memory translation buffer configured to manage (i) a first request for a first search in a page table, wherein the first request is responsive to a first null result of a search for a first address translation in a translation look-aside buffer (“TLB”) and (ii) a second request for a second search in the page table, wherein the second request is responsive to a second null result of a search for a second address translation in the TLB. The memory translation buffer is also configured to compare a virtual memory address of the first request to a virtual memory address of the second request and, based on a result of the comparing the virtual memory address of the first request to the virtual memory address of the second request, access the page table to perform the second search.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.