Third party component debugging for integrated circuit design
US9619600B2 · kind B2 · utility
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31References
16Claims
0Family size
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Key dates
| Filing date | Sep 19, 2014 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Sep 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The application is directed towards facilitating the debugging of suspected errors in a proprietary component when the proprietary component is incorporated into a larger electronic design. Various implementations provide for the generation of a reference model for an integrated circuit design, where the reference model includes the proprietary component and sufficient information about the rest of the design to allow for the debugging of the proprietary component over a period of verification where the error in the proprietary component is suspected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.