Memory provided with associated volatile and non-volatile memory cells
US9620212B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | Jan 7, 2015 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Jan 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array including: a plurality of volatile memory cells, each including a latch; and a plurality of non-volatile memory cells, each including at least one resistive element that can be programmed by the direction of a current passed therethrough in order to take at least two resistive states, each of the non-volatile memory cells being associated with a corresponding cell from the volatile memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.