Stacked protection devices with overshoot protection and related fabrication methods
US9620496B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2015 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | May 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
Protection circuits, device structures and related fabrication methods are provided. An exemplary protection circuit includes a first protection arrangement and a second protection arrangement. The first protection arrangement includes a first transistor having a first collector, a first emitter, and a first base coupled to the first emitter at a first node, and a second transistor having a second collector, a second emitter, and a second base coupled to the second emitter at a second node, the second collector being coupled to the first collector at a third node. The second protection arrangement is coupled electrically in series between the second node and a fourth node. The protection circuit further includes a first diode coupled between the third node and the fourth node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.