Electrostatic discharge (ESD) control circuit
US9620957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2013 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Apr 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
One or more electrostatic discharge (ESD) control circuit are disclosed herein. In an embodiment, an ESD control circuit has first and second trigger transistors, first and second ESD transistors, and first and second feedback transistors. The ESD transistors provide ESD current paths for ESD current generated during an ESD event. The first and second trigger transistors are on during normal operation to maintain the ESD transistors in an off state. During an ESD event, the first and second transistors are turned off to enable the first and second ESD transistors to provide ESD current paths. The first and second feedback transistors turn on during an ESD event to reinforce the on state of the ESD transistors and to reinforce the off state of the trigger transistors. In this way, the ESD control circuit stably provides multiple ESD current paths to discharge ESD current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.