Active load circuit and semiconductor integrated circuit
US9621116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2015 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Sep 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45424
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, there is provided an active load circuit including a first transistor, a second transistor, a first resistor, a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a line. The third transistor is placed between the first transistor and the first reference node. The fourth transistor is placed between the second transistor and the first reference node. The seventh transistor is placed between the fifth transistor and the first reference node. The eighth transistor is placed between the sixth transistor and the first reference node. A line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.