Patent · US Active

Method and apparatus for generating systolic arrays on a target device using a high-level synthesis language

US9626165B1 · kind B1 · utility

4Cited by
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25Claims
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Assignee

Inventor

  • Yi Ni · Heidelberg, DE

Key dates

Filing dateSep 12, 2013
Grant dateApr 18, 2017
Priority date—
Expiry dateDec 21, 2034

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F30/327
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method for generating a description of a systolic array includes prompting a user to input information about the systolic array. A high-level synthesis language is generated that describes channels of processing elements of the systolic array and a topology of the processing elements in response to the information provided by the user.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.